1. Field of the Invention
The present invention relates to an electro static discharge protection circuit, and particularly, to an electro static discharge protection circuit which is suitable for reducing a pitch between pads by discharging static electricity using a low-voltage mos-transistor in a circuit using high voltage.
2. Description of the Background Art
Generally, in case of high voltage process higher than 12V used in a field related to a display such as LCD (Liquid Crystal Display), OEL (Organic Electro Luminant), and PDP (Plasma Display Panel), a high voltage mos-transistor is used as a mos-transistor for discharging electro static applied to a pad. The high-voltage mos-transistor like above is larger than a low-voltage mos-transistor, and accordingly, the size of the electro static discharge protection circuit and a chip size are increased. In addition, pitches between pads in the chip including a plurality of pads should be increased, and therefore, it is difficult to construct a circuit.
Hereinafter, the electro static discharge protection circuit using the high-voltage mos-transistor will be described in more detail with reference to accompanying figures.
FIG. 1 is an exemplary circuit diagram of an electro static discharge protection circuit using the high-voltage mos-transistor according to the conventional art, as shown therein, the electro static discharge protection circuit comprises: a first high-voltage pmos-transistor (HCPM1) and a first high-voltage nmos-transistor (HVNM1), in which a drain terminal is connected to a first pad (PAD1) respectively and a source terminal and a gate terminal are commonly connected, respectively; and a second high-voltage pmos-transistor (HVPM2) and a second high-voltage nmos-transistor (HVNM2), in which a drain terminal is connected to a second pad (PAD2), and a source terminal and a gate terminal are commonly connected, respectively.
Herein, the first high-voltage pmos-transistor (HVPM1) and the first high-voltage nmos-transistor (HVNM1) which are commonly connected to the first pad (PAD1) are corresponded to the second high-voltage pmos-transistor (HVPM2) and the second high-voltage nmos-transistor (HVNM2) which are commonly connected to the second pad (PAD2).
An operation of the conventional electro static discharge protection circuit using the high-voltage mos-transistor constructed as above will be described as follows.
When the electro static is applied to the first pad (PAD1), the first high-voltage pmos-transistor (HVPM1) and the first high-voltage nmos-transistor (HVNM1) are turned on to make a current by the high-voltage flow on the two transistors. At that time, the operating states of the first high-voltage pmos-transistor (HVPM1) and of the first high-voltage nmos-transistor (HVNM1) are decided by the size of the voltage which is applied to the first pad (PAD1). That is, the transistor are turned on only when the voltage applied to the first pad (PAD1) is same or larger than a predetermined value.
For example, in case of a system using voltage higher than 12V, an inner circuit is protected by being turned on by the voltage higher than 12V not to make the current by the electro static flow on the inner circuit. That is, the current by the electro static applied through the first high-voltage pmos-transistor (HVPM1) and the first nmos-transistor (HVNM1) is applied to the source terminal and the gate terminal of the second high-voltage pmos-transistor (HVPM2) and of the second high-voltage nmos-transistor (HVNM2), and accordingly, the second high-voltage pmos-transistor (HVPM2) and the second high-voltage nmos-transistor (HVNM2) are turned on. In addition, the current by the electro static is discharged through the second pad (PAD2) to protect the inner circuit.
At that time, the sizes of the respective first and second pmos-transistors (HVPM1 and HVPM2), and of the first and second high-voltage nmos-transistors (HVNM1 and HVNM2) are greatly increased comparing to a low voltage mos-transistor which is generally used, and accordingly, the size of the pad is greatly increased.
However, some display IC (Integrated Circuit) can not use the above pad because it needs a plurality of signal pins.
If a part of the electro static discharge protection circuit is reduced in order to solve the above problem, an immunity of the electro static discharge protection circuit is greatly decreased to harm a reliability of the IC fatally. That is, even the IC performs normal operation, the IC may be disused due to unstable operation of the electro static discharge protection circuit. For example, in case of the high-voltage nmos-transistor used in the electro static discharge protection circuit shown in FIG. 1, the width is 400 xcexcm and the length is 3 xcexcm in 0.6 xcexcm/16V specification, and the width is 500 xcexcm and the length is 3 xcexcm in 0.35 xcexcm/18V specification.
However, in case of low-voltage mos-transistor, the length is 0.6 xcexcm in 0.6/16V specification, and the length is 0.35 xcexcm in 0.35 xcexcm/18V. In addition, the width is also greatly reduced.
FIG. 2 is an exemplary view showing disposition of the pad in the electro static discharge protection circuit according to the conventional art, the area in which the high-voltage mos-transistor constituting the electro static discharge protection circuit is larger than the size of the pads (PAD1 and PAD2), and accordingly, the pitches P between the pads (PAD1 and PAD2) can not be narrowed less than a predetermined distance.
In case that the low-voltage mos-transistor is used in order to solve the problem of the high-voltage mos-transistor, a breakdown voltage of the low-voltage mos-transistor is greatly lowered. Therefore, the low-voltage mos-transistor is not able to function as the electro static discharge protection circuit. In that case, in order to make the low-voltage mos-transistor endure the high breakdown voltage, the circuit should be disposed as shown in FIG. 3.
FIG. 3 is an exemplary view showing a cascade-mos pad using the low-voltage mos-transistor, and the cascade-mos pad comprises a top nmos (LVNM1) and a bottom nmos (LVNM2).
In that case, the size of the transistor is small, however, the area is not greatly reduced because the number of transistors is increased.
As described above, according to the conventional electro static discharge protection circuit, the size of the circuit is increased by using the high-voltage transistor in high-voltage process, and the pitch between pads are increased, and thereby entire degree of integration is lowered.
Therefore, an object of the present invention is to provide an electro static discharge protection circuit in which an electro static is discharged using a low voltage mos-transistor in a circuit using high voltage, and a pitch between pads can be effectively reduced.
To achieve the object of the present invention, as embodied and broadly described herein, there is provided an electro static discharge protection circuit comprising: a first pad; a second pad; and a low-voltage nmos-transistor unit connected between the first and the second pads.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.